In order to minimize processing errors, maximize throughput by reducing the amount of time it takes to manufacture a given number of integrated circuit (IC) chips, and ease of handling considerations, a large number of IC chips are processed simultaneously on the surface of a wafer before the wafer is cut or “diced” into the individual chips. However, the dicing process may cause cracks in the active (wired) areas of the IC chips, thus resulting in chip failure. To reduce the amount of chip failure due to crack propagation during dicing and the resultant device failure, several processes have been developed including: a “free space” crack stop; a dicing channel; removing metal from the dicing channel; using a narrower dicing blade; and implementing an additional inspection process to reject damaged chips.
The following references relate to various examples of attempts to prevent cracking of chips. They are included as general interest.
U.S. Pat. No. 7,163,883 (Agarwala et al), issued Jan. 16, 2007, discloses an edge seal around the periphery of an integrated circuit device. The edge seal protects the copper circuitry from cracks that can form in the low-k interlevel dielectric layer during chip dicing. The edge seal comprises a dielectric wall between the copper circuitry and the low-k dielectric near the periphery of the IC device; the dielectric wall being of a different material than the low-k interlevel dielectric.
U.S. Patent Application Publication 2005/0026397 (Daubenspeck et al), published Feb. 3, 2005, relates to a crack stop for a low-k dielectric material of an integrated circuit formed on an IC chip. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the barrier/seal on the outer periphery of the IC chip.
U.S. Pat. No. 5,834,829 (Dinkel et al), issued Nov. 10, 1998, discloses an energy relieving crack stop which is redundant. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization. It also provides for a greater surface area over which the crack producing energy may spread. In the manufacturing process, the redundant crack stop is produced during the metallization process.
U.S. Pat. No. 6,972,209 (Agarwala et al), issued Dec. 6, 2005, relates to a multilevel semiconductor integrated circuit structure. Each layer of dielectric material includes at least one layer of low-k dielectric material. A set of stacked via studs is present in the layer of low-k dielectric material. The set of stacked via studs increases resistance to thermal fatigue crack formation.
U.S. Patent Application Publication 2005/0208781 (Fitzsimmons et al), published Sep. 22, 2005, and U.S. Pat. No. 7,109,093 (Fitzsimmons et al), issued Sep. 19, 2006, disclose methods of formation of an integrated circuit device structure. The structure has vertical interfaces adjacent crack stops around the perimeter of the chip. The vertical interfaces comprise vertical spacers of release materials, vertical trenches of release material or vertical channels of the release material. The vertical interfaces can act by: deflecting cracks away from the penetrating crack stop, absorbing the generated crack energies, or allowing the advancing cracks to lose energy such that they become incapable of penetrating the crack stop.
None of the references cited above, either separately or in combination, anticipate the inventive features of the present disclosure.
A process that would be simple and inexpensive, and would reliably prevent crack propagation into the active areas of the chips during the dicing process is therefore desirable.